The present invention relates to current mirrors, and more particularly, to output current mirrors for use with transconductor circuits.
It is known to provide current mirrors which include two transistors as shown in FIG. 1. In such a current mirror, transistor N1 is diode connected. The gate of transistor N1 is connected to the gate and drain of transistor N2, thus forcing the same gate to source voltage on both N1 and N2. If transistor N1 is in the "saturated" mode of operation (i.e., V.sub.ds of N1 is &gt;V.sub.gs - V.sub.t of N1 where V.sub.ds is the drain to source voltage, V.sub.gs is the gate to source voltage, and V.sub.t is the threshold voltage) the current into the drain node of N1 is ideally proportional to the current into the drain node of N2 by the ratio of the transistor's gate widths and inversely proportional to the transistor's gate lengths. However, when there is a threshold mismatch, i.e., the threshold voltage of N1 is not equal to the threshold voltage of N2, there arises serious distortion in the drain current of N1 with respect to the input current in the drain of N2. Typically, 1 to 2 millivolts of threshold mismatch between transistors N1 and N2 can produce distortion levels of -60 dB or more.
Current mirrors are required in the design of high linearity, low distortion, continuous time transconductors in CMOS. A transconductor is a circuit which receives an input voltage and generates an output current. The magnitude of the output current is proportional to the input voltage received; the ratio by which the output current changes for a given ratio of input voltage change is known as the conversion gain, or transconductance (GM), of the transconductor. A differential transconductor receives a differential voltage impressed between two input terminals (ignoring the common-mode voltage) and generates a differential current on two current output terminals.
A differential transconductor 20 which is known in the art is shown in FIG. 2. The topology of this circuit is generally known as a degenerated pair linearized by servo-feedback. A differential input voltage, V.sub.L -V.sub.R, is received on input terminals 22, 24 and a corresponding differential current is generated at current output terminals 26, 28. Transconductor 20 includes current source circuit 30 as well as input circuits 32, 34. Current source circuit 30 includes current sources 36, 37 which provide currents in the amount of I.sub.o to summing nodes 38, 39, respectively. Input circuit 32 includes operational amplifier 40 having a non-inverting input coupled to input voltage terminal 22 and an inverting input coupled to summing node 38. The output of operational amplifier 40 drives the gate of transistor 42, which in this embodiment is shown as a P channel MOS transistor. Transistor 42 couples summing node 38 to current output terminal 26. Input circuit 34 includes operational amplifier 50 having a non-inverting input terminal coupled to input voltage terminal 24 and an inverting input terminal coupled to summing node 39. The output of operational amplifier 50 drives the gate of transistor 52, which is also shown as a P channel MOS transistor. Transistor 52 couples summing node 39 to current output terminal 28. Transconductor 20 also includes resistor 54 having a resistance of R ohms. Resistor 54 couples summing node 38 to summing node 39. Current output terminals 28, 29 are coupled to respective current mirrors 56, 57, which in turn provide differential current outputs I.sub.L ' and I.sub.R ' to current mirror current output terminals 58, 59. Current mirrors 56, 57 are similarly configured to provide output currents having the same ratio to the currents which are provided to the respective current mirrors.
The operation of this circuit can best be understood by reference to the left portion of the transconductor. Input circuit 32 forces the voltage of summing node 38 to follow the voltage, V.sub.L, received on input voltage terminal 22. This occurs because operational amplifier 40 drives the gate of transistor 42 to a suitable voltage such that the voltage of summing node 38, which is coupled to the inverting input of operational amplifier 40, follows the voltage, V.sub.L, coupled to the non-inverting input of operational amplifier 40. Similarly, with respect to the right portion of the transconductor, input circuit 34 forces the voltage of summing node 39 to follow voltage, V.sub.R, received on input voltage terminal 24. This occurs because operational amplifier 50 drives the gate of transistor 52 to a suitable voltage such that the voltage of summing node 39, which is coupled to the inverting input of operational amplifier 50, follows the voltage V.sub.R coupled to the non-inverting input of operational amplifier 50. Thus, with summing node 38 following input voltage V.sub.L and summing node 39 following input voltage V.sub.R, the differential input voltage V.sub.L -V.sub.R is placed across resistor 54, and causes a current, I.sub.s, of magnitude (V.sub.L -V.sub.R)/R to flow from summing node 38 to summing node 39. If V.sub.R is greater in magnitude than V.sub.L, then a negative current I.sub.s flows from summing node 38 to summing node 39 which, of course, is equivalent to a positive current flow from summing node 39 to summing node 38.
Summing node 38 receives a current I.sub.o from current source 36 and sources a current I.sub.s flowing into summing node 39. Thus, the net current provided to the source of transistor 42 is I.sub.o -I.sub.s, which is coupled via transistor 42 to current output terminal 26. Similarly, summing node 39 receives a current I.sub.o from current source 37, and receives a current I.sub.s flowing from summing node 38. Thus, the net current supplied to the source of transistor 52 is I.sub.o +I.sub.s, which is coupled via transistor 52 to current output terminal 28. Current output terminals 26, 28 provide respective currents I.sub.L and I.sub.R to current mirrors 56, 57 which provide output currents I.sub.L ' and I.sub.R ' to current mirror current output terminals 58, 59. Currents I.sub.L ' and I.sub.R ' are proportional to the currents I.sub.L and I.sub.R.
In this transconductor, transistor N2 of the current mirrors 56, 57 has a drain to source voltage equal to the threshold voltage of the transistor plus an excess voltage related to the square root of the current into the drain of transistor N2 and its gate width and gate length. Accordingly, the threshold voltage present at the current output terminals of the transconductor is limited by this configuration
In transconductors which use current mirrors implemented using BiCMOS or Bipolar technologies, the inherent V.sub.BE matching of bipolar transistors produces a high linearity current mirror which does not add distortion to the transconductor output. However, in transconductors which are implemented using CMOS technologies such as that shown in FIG. 1, a current mirror which is located at the output of the transconductor may provide a source of distortion. One challenge with designing current mirrors is that the normal process variations of the threshold voltages, V.sub.t, between two MOS devices which are used in a current mirror may prevent design of a low distortion transconductor.